Computer Organization and Architecture Mock Test 10

10%

Question 1 of 10

1. The instructions in 68000 can deal with operands of three different sizes.

True

False

Question 1 of 10

Question 2 of 10

2. The effective address of the instruction written in Post-indexed mode, MOVE[Rn]+Rm is _______

EA = [Rn] + Rm

EA = [Rn]

EA = [Rn + Rm]

EA = [Rm] + Rn

Question 2 of 10

Question 3 of 10

3. The instruction, ADD R1, R2, R3 is decoded as ___________

R3<-[R1]+[R2]+[R3]

R1<-[R2]+[R3]

R3<-[R1]+[R2]

R1<-[R1]+[R2]+[R3]

Question 3 of 10

Question 4 of 10

4. As the instructions can deal with variable size operands we use ____________ to resolve this.

None of the mentioned

Delimiter

Size indicator mnemonic

Special assemblers

Question 4 of 10

Question 5 of 10

5. The 68000 uses _____ address assignment.

X-Big Endian

Little Endian

Big Endian

X-Little Endian

Question 5 of 10

Question 6 of 10

6. The Instruction, LDM R10!, {R0,R1,R6,R7} ______

Creates a copy of the contents of R10 in the other registers except for the above mentioned ones

Loads the contents of the registers R1, R0, R6 and R7 to R10

Loads the contents of R10 into R1, R0, R6 and R7

Writes the contents of R10 into the above mentioned registers and clears R10

Question 6 of 10

Question 7 of 10

7. The ability to shift or rotate in the same instruction along with other operation is performed with the help of _________

Switching circuit

Barrel switcher circuit

Integrated Switching circuit

Multiplexer circuit

Question 7 of 10

Question 8 of 10

8. The offset used in the conditional branching is __________ bit.

Question 8 of 10

Question 9 of 10

9. The size of the floating registers can be extended upto _________

128 bit

64 bit

80 bit

256 bit

Question 9 of 10

Question 10 of 10

10. The status register of the 68000 has ____ condition codes.

Question 10 of 10