Digital Circuits Mock Test 7

10%

Question 1 of 10

1. Ripple counter IC has _____________

14 pins

12 pins

11 pins

10 pins

Question 1 of 10

Question 2 of 10

2. The main drawback of a ripple counter is that __________

It has a productive settling time

It has a distributive settling time

It has a cumulative settling time

It has an associative settling time

Question 2 of 10

Question 3 of 10

3. Fundamental mode is another name for ____________

Pulse operation

Clock operation

Edge operation

Level operation

Question 3 of 10

Question 4 of 10

4. Normally, the synchronous counter is designed using ____________

D flip-flops

T flip-flops

J-K flip-flops

S-R flip-flops

Question 4 of 10

Question 5 of 10

5. In DOWN-counter, each flip-flop is triggered by ___________

The output of the next flip-flop

The inverted output of the preceding flip-flop

The clock pulse of the previous flip-flop

The normal output of the preceding flip-flop

Question 5 of 10

Question 6 of 10

6. In an UP-counter, each flip-flop is triggered by ___________

The clock pulse of the previous flip-flop

The normal output of the preceding flip-flop

The output of the next flip-flop

The inverted output of the preceding flip-flop

Question 6 of 10

Question 7 of 10

7. Three cascaded decade counters will divide the input frequency by ____________

100

1000

Question 7 of 10

Question 8 of 10

8. The ________ counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.

AHDL

74134

LPM

Synchronous

Question 8 of 10

Question 9 of 10

9. How many types of registers are?

Question 9 of 10

Question 10 of 10

10. UP-DOWN counter is also known as ___________

Two Counter

Multimode counter

Dual counter

Multi counter

Question 10 of 10