Digital Circuits Practice Test 6

1. When both inputs of a J-K flip-flop cycle, the output will ___________

2. The S-R latch composed of NAND gates is called an active low circuit because _____________

3. What is one disadvantage of an S-R flip-flop?

4. When a high is applied to the Set line of an SR latch, then ___________

5. Which of the following is the Universal Flip-flop?

6. Whose operations are more faster among the following?

7. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the _____________

8. In D flip-flop, if clock input is LOW, the D input ___________

9. Both the J-K & the T flip-flop are derived from the basic _____________

10. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?