Microprocessor Mock Test 8

10%

Question 1 of 10

1. The data type, "one quad word" packs __________ into 64-bit.

one 32-bit and two 16-bit quantities

four 16-bit words

one single 64-bit quantity

two 32-bit quantities

Question 1 of 10

Question 2 of 10

2. The floating point multiplier segment performs floating point multiplication in

double precision

extended precision

single precision

all of the mentioned

Question 2 of 10

Question 3 of 10

3. The number of double words that can be packed into 64-bit register using packed double word is

Question 3 of 10

Question 4 of 10

4. In fetch-decode unit, the number of parallel decoders that accept the stream of fetched instructions and decode them is

Question 4 of 10

Question 5 of 10

5. In complex instructions, when the instruction needs to be translated into more than 4 micro-operations, then the decoder transfers the task to

front end branch predictor

trace cache

none

microcode ROM

Question 5 of 10

Question 6 of 10

6. The instructions that pass through the fetch, decode and execution stages sequentially is known as

non-linear instruction sequencing

linear instruction sequencing

sequence of fetch, decode and execution

sequential instruction

Question 6 of 10

Question 7 of 10

7. The instruction or segment that executes the floating point square root instructions is

floating point square root segment

none of the mentioned

floating point division and square root segment

floating point divider segment

Question 7 of 10

Question 8 of 10

8. The compiler reorders the sequential stream of code that is coming from memory into a fixed size instruction group in

super scalar architecture

very long instruction word architecture

super pipelined architecture

multiple instruction issue

Question 8 of 10

Question 9 of 10

9. The MMX instruction, EMMS consists of __________ on which it operates.

destination operand

source and destination operand

source operand

none of the mentioned

Question 9 of 10

Question 10 of 10

10. The unit that subjects the processor operation to boundary scan tests is

segmentation unit

prefetcher unit

parity generation and control unit

boundary scan and control unit

Question 10 of 10