Microprocessor Mock Test 9

10%

Question 1 of 10

1. The unit that predicts the locations from where the next instruction bytes are fetched is

front end branch predictor

trace cache

execution module

instruction decoder

Question 1 of 10

Question 2 of 10

2. If the external interrupt sources control the flags IE0 and IE1, then the interrupt programmed is

edge-sensitive

level-sensitive

in serial port

in parallel port

Question 2 of 10

Question 3 of 10

3. The unit that does not store the instructions, but the decoded stream of instructions is

microcode ROM

front end branch predictor

none

trace cache

Question 3 of 10

Question 4 of 10

4. If the logical processors want to execute complex IA-32 instructions simultaneously then the number of microcode instruction pointers required is

Question 4 of 10

Question 5 of 10

5. After the micro-ops are issued by the microcode ROM, the control goes to

execution module

instruction decoder

trace cache

front end branch predictor

Question 5 of 10

Question 6 of 10

6. A logical processor may be temporarily stalled for

including servicing cache misses

waiting for results of previous instructions

handling branch mispredictions

all of the mentioned

Question 6 of 10

Question 7 of 10

7. The dynamic branch prediction algorithms use

None

Branch History Table (BHT)

Branch Target Buffer (BTB)

Branch History Table and Branch Target Buffer

Question 7 of 10

Question 8 of 10

8. The instruction that is used when either of the logical processors is idle is

HLDA

HOLD

HALT

NONE

Question 8 of 10

Question 9 of 10

9. The hyperthreading technology automatically involves the

none

decrease of die area

increase of die area

decrease of die area to half

Question 9 of 10

Question 10 of 10

10. The instructions that instruct the processor to make a decision about the next instruction to be executed are

none

branch instructions

data dependency instructions

control transfer instructions

Question 10 of 10