VHDL Mock Test 1 - Sanfoundry

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Question 1 of 10

1. What are the differences between simulation tools and synthesis tool?

Simulators are used just to check basic functionality of the circuit and Synthesis tools includes timing constraints and other factors along with simulation

Simulation finds the error in the code and Synthesis tool corrects the code

Simulators are used to check the performance of circuit and Synthesis tools are for the fabrication of circuits

Simulators and Synthesis tools works exactly same

Question 1 of 10

Question 2 of 10

2. An ASIC can be correctly designed by using programming languages like C or Assembly.

True

False

Question 2 of 10

Question 3 of 10

3. Which of the following option is completely legal, given that a and b are two UNSIGNED type signals?

x <= a OR b; y <= a AND b;

x <= a + b; y <= a – b;

x <= a OR b; y <= a + b;

x <= a + b; y <= a OR b;

Question 3 of 10

Question 4 of 10

4. An entity can have more than one architecture.

True

False

Question 4 of 10

Question 5 of 10

5. Which of the following is an entity declared for a full adder?

ENTITY full_adder
    PORT(a, b, c : IN BIT;
    s, co : OUT BIT);
   END full_adder;

ENTITY full_adder IS
    PORT(a, b, c : IN BIT;
    s, co : OUT BIT);
   END full_adder;

ENTITY full_adder IS
    PORT (a, b, c, s, co : BIT);
    END full_adder;

ENTITY full_adder IS
    PORT (a ,b : IN BIT;
    s, c : OUT BIT);
    END full_adder;

Question 5 of 10

Question 6 of 10

6. Which of the following is not a back end EDA tool?

Placement tools

Routing tools

Simulators

Floor planning tools

Question 6 of 10

Question 7 of 10

7. Which of the following is a characteristic of Verilog HDL?

Strongly typed language

Not portable

Better library

Case sensitive

Question 7 of 10

Question 8 of 10

8. Which of the following is the correct architecture for a simple Nand gate?

ARCHITECTURE nand OF nand_gate IS
    BEGIN
    x <= a NAND b;
    END nand;

ARCHITECTURE my_arch OF nand_gate IS
    BEGIN
    x <= a NAND b;
    END my_arch;

BEGIN
    ARCHITECTURE behavioral OF nand_gate IS
    x <= a NAND b;
    END my_arch;

BEGIN
     ARCHITECTURE my_arch OF nand_gate IS
    x <= a NAND b;
    END behavioral;

Question 8 of 10

Question 9 of 10

9. Which of the following mode of the signal is bidirectional?

BUFFER

OUT

INOUT

Question 9 of 10

Question 10 of 10

10. What does the architecture of an entity define?

External interface

Internal functionality

Specifications

Ports of the entity

Question 10 of 10