My Report

VHDL Mock Test 10


Correct Answer: 2 points | Wrong: -1 point
Grades: A* (100% score) | A (80%-99%) | B (60%-80%) | C (40%-60%) | D (0%-40%)
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 10%

Question 1 of 10

1. Which modelling is used in the top-level system design?

Question 1 of 10

Question 2 of 10

2. In designing a 2 to 1 demultiplexer with input d, output y and select line s, which of the following is a correct process statement?

Question 2 of 10

Question 3 of 10

3. How many levels of abstraction are there in the top-level system design?

Question 3 of 10

Question 4 of 10

4. How many types of procedural assignments are there?

Question 4 of 10

Question 5 of 10

5. Moore machine output is synchronous.

Question 5 of 10

Question 6 of 10

6. Which of the following line of the code contains an error?

L1: ARCHITECTURE mux1 OF mux IS
L2: BEGIN
L3: y<= x0 WHEN x = ‘0’ ELSE
L4:   <= x1 WHEN x = ‘1’;
L5: END mux1;

Question 6 of 10

Question 7 of 10

7. What is the first state of FSM?

Question 7 of 10

Question 8 of 10

8. Which of the following tool performs logic optimization?

Question 8 of 10

Question 9 of 10

9. In serial input serial output register, the data of ______ is accessed by the circuit.

Question 9 of 10

Question 10 of 10

10. What kind of output does mealy machine produce?

Question 10 of 10


 

Manish Bhojasia - Founder & CTO at Sanfoundry
Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

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