My Report

VHDL Mock Test 8


Correct Answer: 2 points | Wrong: -1 point
Grades: A* (100% score) | A (80%-99%) | B (60%-80%) | C (40%-60%) | D (0%-40%)
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 10%

Question 1 of 10

1. What is the correct syntax to define a function which overloads any operator, say + operator for bit_vector type?

Question 1 of 10

Question 2 of 10

2. RANGE keyword is always used in _______

Question 2 of 10

Question 3 of 10

3. Which of the following is a reserved word, which may be used to terminate a loop?

Question 3 of 10

Question 4 of 10

4. Impure is a type of _______

Question 4 of 10

Question 5 of 10

5. For what purpose in the following, one can use alias?

Question 5 of 10

Question 6 of 10

6. There are _______ types of GENERATE statement in VHDL.

Question 6 of 10

Question 7 of 10

7. It is necessary to define entity and configuration in the same library.

Question 7 of 10

Question 8 of 10

8. Which of the following is the correct syntax to define a qualified expression?

Question 8 of 10

Question 9 of 10

9. Which of the following keyword is not associated with arrays?

Question 9 of 10

Question 10 of 10

10. What is the correct syntax for FOR generate statement?

Question 10 of 10


 

Manish Bhojasia - Founder & CTO at Sanfoundry
Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

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