My Report

VHDL Mock Test 9


Correct Answer: 2 points | Wrong: -1 point
Grades: A* (100% score) | A (80%-99%) | B (60%-80%) | C (40%-60%) | D (0%-40%)
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 10%

Question 1 of 10

1. What logic circuit is described by the following code?

ARCHITECTURE gate OF my_gate IS
BEGIN
WITH ab SELECT
y<= 0 WHEN “01” OR “10”;
        1 WHEN OTHERS;
END gate;

Question 1 of 10

Question 2 of 10

2. Generally, structural modeling is used with another modeling style.

Question 2 of 10

Question 3 of 10

3. Which of the following doesn't corresponds to NAND gate?

Question 3 of 10

Question 4 of 10

4. Which of the following input on a flip-flop has control over the outputs?

Question 4 of 10

Question 5 of 10

5. What is the VHDL code for the logical function AB’C + ABC + BC?

Question 5 of 10

Question 6 of 10

6. What is the minimum number of NAND gates required to implement an EXOR gate?

Question 6 of 10

Question 7 of 10

7. What is the type of modeling used in the code given below?

ARCHITECTURE my_arch OF my_design IS
BEGIN
y <= ‘1’ WHEN a =’1’ AND b = ‘0’;
       ‘0’ WHEN OTHERS;
END my_arch;

Question 7 of 10

Question 8 of 10

8. Which of the following line is correct for detecting positive edge of a clock?

Question 8 of 10

Question 9 of 10

9. Which of the following is NOT an advantage of asynchronous reset?

Question 9 of 10

Question 10 of 10

10. Which of the following is an advantage of a synchronous reset?

Question 10 of 10


 

Manish Bhojasia - Founder & CTO at Sanfoundry
Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

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