VHDL Practice Test 10

1. What is the first step in writing the VHDL for an FSM?

2. How many levels of abstraction are there in the top-level system design?

3. Four bits shift register enables shift control signal in how many clock pulses?

4. Register data types and memory data types are updated by procedural assignments.

5. Shift registers comprise of which flip-flops?

6. ‘shift_reg’ is used to initialize the _____________ in the shift register.

7. RTL mainly focuses on describing the flow of signals between ________

8. In __________ counter universal clock is not used.

9. What is the first state of FSM?

10. What is the function of the below code?

ENTITY my_logic IS
PORT (din : STD_LOGIC_VECTOR(7 DOWNTO 0);
             Count : STD_LOGIC_VECTOR(3 DOWNTO 0));
END my_logic;
ARCHITECTURE behavior OF my_logic IS
BEGIN
Count <= “0000”
PROCESS(din)
BEGIN
L1: FOR i IN 0 TO 7 LOOP
IF(din(i) = ‘1’) THEN
Count = count+1;
ELSE
NEXT L1;
END LOOP;
END PROCESS;
END behavior;