VHDL Practice Test 2

1. Which of the following is the correct syntax to convert INTEGER ‘p’ into SIGNED number of ‘b’ bits?

2. Which of the following is not the application of inertial delay?

3. What is the use of shift operators?

4. Which of the following is correct declaration for a generic?

5. The condition to implement the simulation delta delay is _______

6. Which of the circuit is described by following VHDL code?

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY my_func IS
PORT(x, a, b : IN std_logic;
q : OUT std_logic);
END my_func;
ARCHITECTURE behavior OF my_func IS
SIGNAL s : INTEGER;
BEGIN
WITH s SELECT
q <= a AFTER 10 ns WHEN 0;
         b AFTER 10 ns WHEN 1;
s <= 0 WHEN x = ‘0’ ELSE
        1 WHEN x = ‘1’;
END behavior;

7. Refer to the VHDL code given below, what should be the output of the identifier ‘y’ and ‘z’?

VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1010;
VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000;
VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000;
…
y := x SRL 2;
z := x SLL 2;
…

8. Which function is used to create a single value for multiple driver signals?

9. In the VHDL code given below, what will be the error at the time of compilation?

TYPE my_int IS INTEGER RANGE -32 TO 32;
TYPE other_int IS INTEGER RANGE 0 TO 100;
SIGNAL x : my_int;
SIGNAL y : other_int;
y <= x + 2;
…

10. The operators like =, /=, <, >, >= are called _________