VHDL Practice Test 3

1. The structural model is similar to___________

2. It is possible to use a GENERIC parameter as a separate component.

3. Which of the following is the correct syntax for component instantiation?

4. There is a special function called interconnect () to define interconnections between pins.

5. Guarded blocks are synthesizable.

6. Which of the following is the right way to leave a port unconnected?

7. Structural style use processes.

8. Which modeling style is used in code given below?

ENTITY design IS
PORT(a, b, c : in BIT;
x, y : out BIT);
END design;
Architecture arch OF design IS
BEGIN
x <= a XOR b XOR c;
y <= (a AND b) OR (b AND c) OR (a AND c);
END arch;
ARCHITECTURE arch1 OF design IS
COMPONENT comp1 IS
PORT (i1, i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
END COMPONENT;
COMPONENT comp2 IS
PORT(a1, a2 : IN STD_LOGIC;
P : OUT STD_LOGIC);
END COMPONENT;
COMPONENT comp3 IS
PORT(d1, d2 : IN STD_LOGIC;
r : OUT STD_LOGIC);
END COMPONENT;
SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC;
BEGIN
X1: comp1 PORT MAP(a, b, s1);
X2 : comp1 PORT MAP(s1, c, x);
X3: comp2 PORT MAP(a, b, s2);
X4 : comp2 PORT MAP(a, c, s3);
X5: comp2 PORT MAP(b, c, s4);
X6: comp3 PORT MAP(s2, s3, s5);
X7: comp3 PORT MAP(s4, s5, y);
END arch1;

9. It is not necessary that the order of the arguments in PORT MAP is taken as the order in which ports are declared.

10. What does modeling type refer to?