My Report

VHDL Practice Test 5


Correct Answer: 2 points | Wrong: -1 point
Grades: A* (100% score) | A (80%-99%) | B (60%-80%) | C (40%-60%) | D (0%-40%)
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1. What is the syntax to use the NEXT statement?

2. Which of the following is correct syntax for defining FOR LOOP?

3. In combinational logic, how many WAIT statements can be used?

4. What is the correct syntax for using a WAIT UNTIL statement?

5. Which of the following is true about WAIT UNTIL statement?

6. Assert statement is a _____________ statement.

7. Which logic circuit is described in the following code?

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY system IS
GENERIC (l : INTEGER := 3);
PORT ( a, b : IN STD_LOGIC_VECTOR ( l DOWNTO 0);
              c     : IN STD_LOGIC;
              x     : OUT STD_LOGIC_VECTOR (l DOWNTO 0)
              y     : OUT STD_LOGIC);
END system;
ARCHITECTURE design OF system IS
BEGIN
PROCESS (a, b, c)
VARIABLE z : STD_LOGIC_VECTOR ( l DOWNTO 0);
BEGIN
z(0) := c;
FOR I IN 0 TO l LOOP
x(i) < = a(i) XOR b(i) XOR z(i);
z(i+1) <= (a(i) AND b(i)) OR (a(i) AND z(i)) OR (b(i) AND z(i));
END LOOP;
y <= z(l);
END PROCESS;
END design;

8. All types of FOR loops are synthesizable.

9. What is the use of REPORT statement?

10. It is not possible to write an infinite loop in VHDL.


 

Manish Bhojasia - Founder & CTO at Sanfoundry
Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

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