VHDL Practice Test 8

1. Which of the following is true about the overloading of ‘+’ and ‘-‘ operators?

They can be defined as binary operators only

They can be defined as either binary or unary operators

They can be defined as ternary operators only

They can be defined as unary operators only

2. Which of the following is a correct statement for IF generate statement?

     IF condition GENERATE
     begin
     declarations;
     concurrent_statements;
     END GENERATE label;

     label : IF condition GENERATE
     declarations;
     begin
     concurrent_statements;
     END GENERATE label;

     IF condition GENERATE
     declarations;
     begin
     sequential_stataements;
     END GENERATE label;

     label : IF condition GENERATE
     declarations;
     begin
     sequential_statements;
     END GENERATE label;

3. Using overloaded subprograms and operators increase readability of code.

False

True

4. AFTER keyword is generally used with which of the following?

Assignment

When

5. Which of the following is the correct syntax for declaring an alias?

ALIAS alias_name : object_name;

ALIAS alias_name - alias_type object_name;

ALIAS alias_name ; object_name;

ALIAS alias_name : alias_type object_name;

6. Which of the following keyword is not associated with arrays?

ARRAY

DOWNTO

GROUP

7. On which side of a signal assignment statement, UNAFFECTED keyword can be used?

Can’t be used in an assignment statement

Left hand side

On any of the side

Right hand side

8. Which of the following keyword is used to identify a clocked process?

No specific keyword

SEQ

CLOCKED

CLKED

9. How does keyword inertial affect an assignment statement?

To prevent overriding of following delay assignment statements

By defining initial value from which delay should be started

No effect

To specify wire delay

10. A qualified expression is synthesizable in VHDL.

False

True