VHDL Practice Test 9

1. Which of the following represents the correct order?

Given function, optimized function, implementation

Optimized function, implementation, given function

Given function, implementation, optimized function

Implementation, optimized function, given function

2. Which of the following line is correct for detecting positive edge of a clock?

IF (clk’EVENT AND clk = ‘0’)

IF (clk’EVENT OR clk = ‘1’)

IF (clk’EVENT OR clk = ‘0’)

IF (clk’EVENT AND clk = ‘1’)

3. Which of the following will reduce the cost of implementation?

Implementing with only one modeling style

Optimization

Generating Net list first

Implementing with dataflow modeling

4. What is the type of modeling used in the code given below?

ARCHITECTURE my_arch OF my_design IS
BEGIN
y <= ‘1’ WHEN a =’1’ AND b = ‘0’;
       ‘0’ WHEN OTHERS;
END my_arch;

Structural

Behavioral

Combinational

Dataflow

5. Preset and clear are asynchronous inputs.

True

False

6. What happens if both the inputs PRE and CLR are activated?

Flip-flop is reset

Flip-flop is set

Invalid State

No output

7. What is the minimum number of NAND gates required to implement an EXOR gate?

8. Reset is a signal that is used for the initialization of the hardware.

False

True

9. What is the state of CLEAR input?

Reset

Don’t care

Invalid

Set

10. Which of the following is the opposite of flattening of functions?

Un-flattening

Structure

Adding intermediate nodes

Factoring